This invention relates generally to semiconductor circuits and more particularly to fabrication of semiconductor circuits having improved thermal transfer characteristics.
As is known in the art, gallium arsenide is a preferred material for high operating frequency and high speed monolithic integrated circuits. In particular, with monolithic microwave integrated circuits, a gallium arsenide substrate supports an active layer in which active devices are provided, and further supports other circuit devices including transmission lines, capacitors, and resistors. These particular circuits may be classified as analog circuits and, therefore, can emcompass the various types of analog circuits including high power circuits. For high power circuits such as power amplifier circuits, an individual heat dissipating device such as a field effect transistor can have a channel temperature which often exceeds 200.degree. C. during operation. In general, the temperature of the device influences the performance, the characteristics, and the reliability of the device. Further, when channel temperatures in transistors exceed 200.degree. C. premature device failure may occur. Therefore, heat must be efficiently removed from the device in order to minimize changes in device performance and the risk of premature failure of the device.
To accomplish this heat removal, typically the backside surface of the substrate, that is, the surface of the substrate, not having formed thereon the active devices is provided with a "heat sink/ground plane" comprised of a highly thermally and electrically conductive material such as gold. Gallium arsenide, however, has a relatively low thermal conductivity in comparison to conductive materials such as gold. Therefore, it would be desirable from a device heat sinking perspective to provide a very thin substrate of gallium arsenide to thereby better effectively remove the heat from the gallium arsenide circuits.
On the other hand, gallium arsenide is also a relatively fragile and mechanically weak material. Therefore, from the perspective of manufacturing and handling, a relatively thick substrate is desirable since it would be less susceptible to damage during manufacturing and handling of the substrate.
Moreover, in many analog circuits, the gallium arsenide substrate acts as a dielectric for strip conductor type transmission lines and, therefore, the thickness of the gallium arsenide substrate is also a consideration from a device properties perspective.
Accordingly, considerations other than the effectiveness of removing heat from heat dissipating elements such as transistors often dictate the thickness of the gallium arsenide substrate. A solution to this problem has been to provide a so-called "tub structure" in which the gallium arsenide is selectively thinned in a region underlying the heat dissipating device providing a region which can be filled with a cnnductive material, to attempt to reduce the thermal resistance between the heat dissipating element and the heat sink/conductive layer formed on the backside of the gallium arsenide substrate.
One problem, however, presented by the formation of this so-called "tub structure" is the difficulty in providing a uniformly thick heat sink layer over the backside of the substrate and conductively filled tub structure. This problem is particularly evident in circuits also having via hole structures. Via hole structures are holes provided completely through the substrate to interconnect with conductors formed on the opposite surface of the substrate or the so-called "frontside" of the substrate. Due to the significant differences in the depths of the tub structure and the depth of the via hole, conventional plating techniques directly replicate these gross topological feature differences in the ground plane.
It would be desirable to provide a substantially uniform and a continuous layer which may be used to mount the semiconductor device on a carrier, for example, and thereby provide a better heat sink and electrical contact with the carrier. A smooth ground plane is desired because, typically, the ground plane portion of the chip is soldered to the chip carrier. However, with the gross topological features replicated in the ground plane, voids or air pockets develop between the tub and the carrier due to incomplete wetting or filling of the voids underlying the tubs with solder when mounting the ground plane portion of the substrate to the carrier. These voids or air pockets result in "hot spots" which can negate any advantages achieved from introduction of the tub structure.